module cmd_dec(
     input         clk       ,
		 input         rst_n     ,
		 input [7:0]   data      ,
		 input         data_valid,
		 output        cmd_valid ,
		 output [15:0] cmd_index ,//指令
		 output [31:0] par_index  //参数

);
localparam DOWN_TIME = 20_000_000;//Time Out
reg [31:0] dwn_cnt ;
reg [7:0]  byte_cnt;
reg        cmd_valid_r0,cmd_valid_r1;
reg [15:0] cmd_index_r;
reg [31:0] par_index_r;
reg [7:0]  data_r[7:0];
assign cmd_valid = cmd_valid_r1;
assign cmd_index = cmd_index_r ;
assign par_index = par_index_r ;
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		cmd_valid_r0 <= 1'b0;
		cmd_valid_r1 <= 1'b0;
		dwn_cnt  <= 0   ;
		byte_cnt <= 8'd0;
		data_r[0] <= 8'd0;
		data_r[1] <= 8'd0;
		data_r[2] <= 8'd0;
		data_r[3] <= 8'd0;
		data_r[4] <= 8'd0;
		data_r[5] <= 8'd0;
		data_r[6] <= 8'd0;
		data_r[7] <= 8'd0;
	end else begin
		dwn_cnt  <= data_valid?DOWN_TIME:dwn_cnt-(|dwn_cnt);
		if(data_valid)begin
			data_r[0] <= data;
			data_r[1]	<= data_r[0];
			data_r[2]	<= data_r[1];
			data_r[3]	<= data_r[2];
			data_r[4]	<= data_r[3];
			data_r[5]	<= data_r[4];
			data_r[6]	<= data_r[5];
			data_r[7]	<= data_r[6];
		end
		else begin
			data_r[0] <= data_r[0];
			data_r[1] <= data_r[1];
			data_r[2] <= data_r[2];
			data_r[3] <= data_r[3];
			data_r[4] <= data_r[4];
			data_r[5] <= data_r[5];
			data_r[6] <= data_r[6];
			data_r[7] <= data_r[7];
		end
		if(data_valid)
			byte_cnt <= (byte_cnt >= 8'd7)?8'd0:byte_cnt+1'b1;
		else if(dwn_cnt == 1)
			byte_cnt <= 8'd0;
		else
			byte_cnt <= byte_cnt;
		cmd_valid_r0 <= data_valid && (byte_cnt >= 8'd7) && (data_r[6] == 8'h44);
		cmd_valid_r1 <= cmd_valid_r0;
		cmd_index_r  <= {data_r[6],data_r[5]};
		par_index_r  <= {data_r[4],data_r[3],data_r[2],data_r[1]};
	end
end
endmodule 